DocumentCode
3581912
Title
60-GHz sub-sampling PLL using a dual-step-mixing ILFD
Author
Siriburanon, Teerachot ; Ueno, Tomohiro ; Kimura, Kento ; Kondo, Satoshi ; Deng, Wei
Author_Institution
Kenichi Okada, and Akira Matsuzawa, Tokyo Institute of Technology, Japan
fYear
2014
Firstpage
708
Lastpage
710
Abstract
This paper presents a 60-GHz sub-sampling PLL using a dual-step-mixing injection-locked frequency divider (ILFD). The sub-sampling operation achieves lower in-band phase noise, and the dual-step-mixing ILFD realizes a low power operation. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It achieves a phase noise of − 115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes only 34mW.
Keywords
Frequency conversion; Frequency synthesizers; Harmonic analysis; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators; 60GHz; CMOS; Millimeter-Wave; PLL; injection-locked frequency divider; sub-sampling;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference (APMC), 2014 Asia-Pacific
Type
conf
Filename
7067921
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