A v-band power amplifier with adaptive bias circuit to save quiescent DC power consumption using 90-nm CMOS technology

A 60 GHz three-stage power amplifier with auto bias control is realized in 90-nm CMOS low-power process. A feed-forward type adaptive bias circuit using an envelope detector is proposed to reduce the dc power consumption in low power operation. This PA provides 13.8-dB linear gain with a quiescent dc power of 100 mW. In high power operating region, it delivers OPidB 11 dBm and 12.7-dBm saturation output power with 168 mW dc power consumption. Compared with fixed bias operation, this technique saves about 40% dc power consumption in low power operating region.