Title :
Configurable hardware implementation of a pipelined DNLMS adaptive filter
Author :
Lee, Raymond ; Khalid, Mohammed A. S. ; Abdel-Raheem, Esam
Author_Institution :
Dept. of Electr. & Comp. Eng., Univ. of Windsor, Windsor, ON, Canada
Abstract :
The delayed normalized least-mean-square (DNLMS) adaptive filtering algorithm is suitable for implementing pipelined architectures. Though previous literature has provided such architectures for DNLMS adaptive filters, none have given a detailed implementation. This paper presents the configurable hardware implementation of a pipelined, modular, low-latency, portable DNLMS adaptive filter which is tested for echo cancellation. The design is implemented onto the Altera Stratix FPGA and has a maximum operating frequency of 32.27 MHz. The design methodology consists of architectural derivation, fixed-point and RTL simulations, physical synthesis, and real-time hardware.
Keywords :
adaptive filters; echo suppression; field programmable gate arrays; least mean squares methods; Altera Stratix FPGA; RTL simulation; configurable hardware implementation; delayed normalized least-mean-square adaptive filtering algorithm; echo cancellation; field programmable gate array; frequency 32.37 MHz; pipelined DNLMS adaptive filter; pipelined architecture; Adaptation models; Adaptive filters; Cascading style sheets; Echo cancellers; Field programmable gate arrays; Finite impulse response filters; Hardware; Adaptive filters; FPGA; echo cancellation;
Conference_Titel :
Microelectronics (ICM), 2014 26th International Conference on
DOI :
10.1109/ICM.2014.7071793
