Low-power burst-mode clock recovery circuit using analog phase interpolator

This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total power consumption as well as design complexity and die area. Verifying functionality of proposed PI-based CRC, the circuit is designed and simulated in 0.18-μm CMOS technology. As simulation results show, the proposed CRC recovers clock at 5GHz in the first unit interval of input data where approximately 40% reduction in power dissipation is achieved. The circuit consumes 2.54mW power from a 1.8-V supply.