DocumentCode
3582375
Title
Memristor-MOS hybrid circuit redundant multiplier
Author
El-Slehdar, A.A. ; Radwan, Ahmed G.
Author_Institution
NISC Res. Center, Nile Univ., Cairo, Egypt
fYear
2014
Firstpage
180
Lastpage
183
Abstract
This paper introduces a step forward towards memristor-MOS hybrid circuit to achieve any combinational function. The proposed design is based on reducing the area by replacing the complete pull-down network with just one memristor and one comparator. The concept is then verified using an example of a simple function. Also, a proposed architecture for memristor based redundant multiplier circuit is introduced and verified using the SPICE simulation. Therefore, any redundant functions can be implemented using the same concept.
Keywords
MIS devices; comparators (circuits); memristor circuits; multiplying circuits; SPICE simulation; combinational function; comparator; memristor based redundant multiplier circuit; memristor-MOS hybrid circuit; pull-down network; Adders; CMOS integrated circuits; Computer architecture; Feeds; Integrated circuit modeling; Memristors; Simulation; Combinational circuits; memristor; mutiplier; redundant;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (ICM), 2014 26th International Conference on
Type
conf
DOI
10.1109/ICM.2014.7071836
Filename
7071836
Link To Document