LVDS receiver with 7mW consumption at 1.5 Gbps

Author

Alqarni, Sultan ; Kamal, Ahmed

Author_Institution

Nat. Center for Electron. & Photonics, King Abdulaziz City for Sci. & Technol. (KACST), Riyadh, Saudi Arabia

fYear

2014

Firstpage

204

Lastpage

207

Abstract

This paper presents an LVDS receiver compatible with ANSI and IEEE standards at 1.5 Gbps. The proposed receiver aims to be compatible with the standard over PVT corners and to have optimized power consumption using 150nm technology with two voltage supplies 3.3 and 1.8V. The receiver design methodology is explained and where is the critical specifications of the standard to be met for other different designs. The presented design consumes 7mW at 1.5Gbps.

Keywords

low-power electronics; radio receivers; telecommunication signalling; ANSI standards; IEEE standards; LVDS receiver; bit rate 1.5 Gbit/s; low-voltage differential signaling; power 7 mW; power consumption optimization; receiver design methodology; size 150 nm; voltage 1.8 V; voltage 3.3 V; Bandwidth; Hysteresis; Receivers; Resistance; Standards; Threshold voltage; Transistors; LVDS; Low Voltage Differential signaling; Receiver; low swing signaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics (ICM), 2014 26th International Conference on

Type

conf

DOI

10.1109/ICM.2014.7071842

Filename

7071842

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3582381