Optimization of voltage-controlled oscillator VCO using current-reuse technique

Optimization of CMOS circuits is essential to reduce power consumption and improve phase noise performance. A novel method to optimize voltage-controlled oscillator VCO is proposed using a current reuse technique. In this paper, three VCO topology for 2.4 GHz application are designed in 0.13μm CMOS process and are simulated using Cadence Spectre. The improvement of the VCO topology is described and analyzed. The traditional current reuse with a tuning range of 14.8% is presented in the first topology. It consumes about 0.267mW from 1V supply voltage. For the second topology, NMOS cross-coupled pair is added to speed up the oscillation and stability .The tuning range and power consumption are 28% and 0.366 mW respectively. It has a high performance of phase noise @ 1MHz with -120 dBc/Hz. The current-reuse oscillator with source degeneration resistance is presented in the third topology. The total power consumption is 0.234mW under 1V supply voltage and the frequency tuning range is 21.8%.