A survey of fault-tolerant processor based on error correction code

Fault detection and correction algorithms has been widely adopted in the various data communication system with view to protect the system from crashing due to hard and soft errors. As the system becomes more complex with the reduction of transistor size, fault detection and correction schemes are not limited to data transfer process. Internal components of the system´s processor are also susceptible to soft errors that potentially would halt the system operation. This paper is focused on the current implementation of error correction code (ECC) on internal processor architecture. Various ECC algorithms are discussed from theory to its operation. Several researches that implemented ECC in processor architecture are also presented in order to demonstrate the variety of ECC execution to the processor architecture. A custom soft-core processor called UTEMRISC is presented as a study case to execute an ECC algorithm in low-end soft-core processor architecture on FPGA platform. For future work, the FT design will be embedded in UTeMRISC03 processor with further analysis of the fault assessment on each of the processor´s components.