A low-power Clock and Data Recovery circuit for 2.5 Gb/s SDH receivers

Author

Pallotta, Andrea ; Centurelli, Francesco ; Trifiletti, Alessandro

Author_Institution

Fiber Opt. Transp. R&D, Siemens ICN, Milan, Italy

fYear

2000

fDate

2000

Firstpage

67

Lastpage

72

Abstract

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f_T silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2²³-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.

Keywords

bipolar integrated circuits; elemental semiconductors; optical receivers; power consumption; silicon; synchronisation; synchronous digital hierarchy; 2.5 Gb/s; 2.5 Gbit/s; 27 GHz; 3.3 V; 3.3 V supply voltage; 350 mW; IC; Maxim GST-2; PLL; SDH receivers; STM-16 systems; Si bipolar technology; clock and data recovery circuit; clock recovery; input sensitivity; power consumption below 350 mW; power dissipation below 0.5 W; rms jitter 10 ps; transimpedance amplifier; Bipolar integrated circuits; Clocks; Energy consumption; Monolithic integrated circuits; Power amplifiers; Power dissipation; Power measurement; Silicon; Synchronous digital hierarchy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Print_ISBN

1-58113-190-9

Type

conf

DOI

10.1109/LPE.2000.155255

Filename

876759