Reusable and design independent memory controller scoreboard using memory data hazard checks

This paper investigates memory data hazard checks as a method to implement a reusable and memory controller design independent scoreboard. A scoreboard architecture that uses memory data hazard checks is proposed and implemented, along with a testbench implementation that uses this scoreboard. The memory data hazard scoreboard and testbench implementation is then evaluated on selected memory controller designs, for functionality, as well as reusability. The evaluation results show scoreboard reusability of 100% is achievable, with testbench reusability of at least 60%, and up to 70%. A qualification process is established to ensure the scoreboard and testbench is functionally correct. From the results, it shows that a properly architected scoreboard and testbench code, once properly qualified, can significantly reduce verification time on subsequent projects.