Energy-efficient 32×32-bit multiplier in tunable near-zero threshold CMOS

An 80,000 transistor, low swing, 32×32-bit multiplier was fabricated in a standard 0.35 μm, V_th=0.5 V CMOS process and in a 0.35 μm, back-bias tunable, near-zero V_th process. While standard CMOS at V_dd=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V_th version at V_dd=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-V_th version is able to run at 188 MHz, which is 38% faster than standard CMOS.