RISC+SIMD=DSP?

Author

Shi, Hao

Author_Institution

Infineon Technol., San Jose, CA, USA

Volume

6

fYear

2000

fDate

6/22/1905 12:00:00 AM

Firstpage

3211

Abstract

The adoptions of RISC (reduced instruction set computer) and SIMD (single instruction multiple data) architectures in processor design have been proven great successes in boosting processor performance. System designers and processor architects are now asking if the combination of both can produce a unified digital signal processor (DSP)/microcontroller (MC) for system-on-a-chip design. The unified processor is particularly suited for cost reduction of handheld systems such as cellular phone and speech interface applications. This paper discusses various aspects that contribute to the answer of this question as well as the top-level design tradeoffs

Keywords

cellular radio; digital signal processing chips; microcontrollers; parallel architectures; reduced instruction set computing; speech-based user interfaces; telephone sets; DSP/microcontroller; Infineon TriCore; RISC architecture; SIMD architecture; cellular phone application; cost reduction; handheld systems; processor design; processor performance; reduced instruction set computer; single instruction multiple data; speech interface application; system-on-a-chip design; top-level design tradeoffs; unified digital signal processor; Boosting; Computer aided instruction; Computer architecture; Digital signal processing; Digital signal processors; Microcontrollers; Process design; Reduced instruction set computing; Signal design; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-6293-4

Type

conf

DOI

10.1109/ICASSP.2000.860083

Filename

860083