Parallel Viterbi algorithm for a VLIW DSP

Author

Khan, Shoub Ahmad ; Saqib, Malik M. ; Ahmed, Sherjil

Author_Institution

Nat. Univ. of Sci. & Technol., Rawalpindi, Pakistan

Volume

6

fYear

2000

fDate

6/22/1905 12:00:00 AM

Firstpage

3390

Abstract

The Viterbi decoder algorithm for a very high data-rate satellite receiver is computationally very intensive. Dedicated commercially available chips are used for high rate convolutional decoders. With the advent of high speed DSPs, these computationally intensive algorithms can be mapped on programmable DSPs running test of the receiver algorithm. This paper presents the Viterbi algorithm specially designed for VLIW DSPs and its implementation on a commercially available DSP for a very high data rate coherent burst demodulator satellite receiver

Keywords

Viterbi decoding; convolutional codes; demodulators; digital signal processing chips; instruction sets; parallel algorithms; parallel architectures; programmable circuits; radio receivers; satellite communication; trellis coded modulation; 4D TCM; VLIW DSP; Viterbi decoder algorithm; coherent burst demodulator satellite receiver; commercially available DSP; dedicated commercially available chips; high data-rate satellite receiver; high rate convolutional decoders; high speed DSP; parallel Viterbi algorithm; programmable DSP; receiver algorithm; trellis coded modulation; Algorithm design and analysis; Communications technology; Decoding; Demodulation; Digital signal processing; Digital signal processing chips; History; Signal processing algorithms; VLIW; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-6293-4

Type

conf

DOI

10.1109/ICASSP.2000.860128

Filename

860128