Title :
Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise
Author :
Kanigicheria, B. ; Oh, Sung-Hun ; Allee, David
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Abstract :
An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated
Keywords :
CMOS integrated circuits; Laplace transforms; VLSI; capacitors; integrated circuit modelling; integrated circuit noise; 0.6 micron; BSIM device; CMOS VLSI system; Laplace transform; analytical model; design; differential equation; on-chip bypass capacitor; switching noise; Capacitors; Circuit noise; Differential equations; Inductors; Noise reduction; Packaging; Semiconductor device modeling; System-on-a-chip; Very large scale integration; Working environment noise;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621473
