Title :
Strategies for automatic synthesis of analog building blocks
Author :
Naess, Sigbjorn ; Lande, Tor Sverre
Author_Institution :
Dept. of Inf., Oslo Univ., Norway
Abstract :
This paper presents a system for automated synthesis of CMOS analog low-power building blocks. The EKV MOST model is used to model the behaviour of the MOS transistor. The concept of partial synthesis is introduced. The feasibility of the method is shown by synthesizing a CMOS low-power delay element. The quality of the synthesis may be verified by comparing the specifications as determined by the synthesis program with simulation results and measurements from a chip
Keywords :
CMOS analogue integrated circuits; circuit CAD; delay circuits; integrated circuit design; CMOS analog low-power building blocks; EKV MOST model; MOS transistor; automatic synthesis; delay element; partial synthesis; Capacitors; Circuit simulation; Circuit synthesis; Delay; Informatics; Integrated circuit synthesis; Operational amplifiers; Semiconductor device modeling; Topology; Voltage;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621475
