Strategies for automatic synthesis of analog building blocks

This paper presents a system for automated synthesis of CMOS analog low-power building blocks. The EKV MOST model is used to model the behaviour of the MOS transistor. The concept of partial synthesis is introduced. The feasibility of the method is shown by synthesizing a CMOS low-power delay element. The quality of the synthesis may be verified by comparing the specifications as determined by the synthesis program with simulation results and measurements from a chip