A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction

Compact Descriptors for Visual Search (CDVS) has been recently proposed as the part of the MPEG-7 standard which encompasses technologies and algorithms for the automatic retrieval of visual information from images and videos. A critical part of these algorithms is the selection of points of interest, also referred to as key points, within the given frame. The extracted features need to exhibit robustness against changes as luminance variations, geometrical transformations, and image rescaling. Such characteristics are typical of feature extraction techniques based on the Scale-Space theory and on the Laplacian-of Gaussian (LoG) kernels. In CDVS, a key point detection algorithm based on filtering with LoG kernels is proposed: being these filters non-separable, filtering in space domain requires the computation of 2D-convolutions, which in turn results in the algorithm being heavily demanding in terms of computational cost when performed in such a domain. As a consequence, we propose a frequency domain approach to CDVS key point extraction, which is at the core of the processor described in this paper. The main drawback connected to frequency domain operation is related to buffering: to reduce this, the proposed processor operates on a block-by-block basis while exploiting the characteristics of the CDVS algorithm to reduce buffering to a minimum. The architecture proposed herein, deployed on an ALTERA Stratix IV FPGA, is capable of extracting key points at a maximum frame rate over 20 fps, proving itself suitable for real-time applications.