DocumentCode
3585646
Title
An improved FPGA-based specific processor for Blokus Duo
Author
Olivito, Javier ; Delmas, Alberto ; Resano, Javier
Author_Institution
gaZ group, Univ. of Zaragoza, Zaragoza, Spain
fYear
2014
Firstpage
366
Lastpage
369
Abstract
This article presents a hardware design of a specific processor for Blokus Duo game. This design is an evolution of our previous work presented in the ICFPT´13 Design Competition. In order to improve its performance we have designed parallel hardware blocks to speed up the most time-consuming tasks, and included additional techniques to reduce the search space. As a consequence we can process a board six times faster than in our previous version and we prune the game-tree much more efficiently.
Keywords
computer games; field programmable gate arrays; logic design; microprocessor chips; Blokus Duo game; FPGA-based specific processor; ICFPT´13 design competition; field programmable gate arrays; game-tree; search space; Field programmable gate arrays; Games; Hardware; Law; Parallel processing; Radiation detectors; Blokus Duo; FPGA; min-max; parallelism;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology (FPT), 2014 International Conference on
Print_ISBN
978-1-4799-6244-0
Type
conf
DOI
10.1109/FPT.2014.7082822
Filename
7082822
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