Title :
Efficient VLSI architecture for FIR filter using DA-RNS
Author :
Kamal, Raj ; Chandravanshi, Piyush ; Jain, Neha ; Rajkumar
Author_Institution :
Dept. of Electron. & Commun. Eng., Jaypee Univ. of Eng. & Technol., Guna, India
Abstract :
In this paper, an efficient multiplier less finite impulse response (FIR) filter architecture based on distributed arithmetic (DA) using high speed residue number system (RNS) is presented. The proposed architecture uses RNS and parallel DA to increase the speed of the system. The proposed architecture is coded in VHDL and synthesized using Synopsys Design Compiler using SAED 90nm CMOS library to calculate area and delay. Synthesis results show that, the proposed structure using DA-RNS has 77.93% less area-delay-product (ADP) than the design proposed by Chan Hua Vun.
Keywords :
CMOS digital integrated circuits; FIR filters; VLSI; distributed arithmetic; integrated circuit design; residue number systems; DA-RNS; FIR filter; SAED CMOS library; Synopsys Design Compiler; VHDL; VLSI architecture; distributed arithmetic; high speed residue number system; multiplier less finite impulse response filter architecture; size 90 nm; Adders; Complexity theory; Delays; Dynamic range; Finite impulse response filters; Table lookup; Distributed arithmetic; FIR filter; Residue number system;
Conference_Titel :
Electronics,Communication and Computational Engineering (ICECCE), 2014 International Conference on
DOI :
10.1109/ICECCE.2014.7086656
