Improve the Verification Productivity: Some Best Practices from SoC and Processor Projects

Author

Weihua Han

Author_Institution

Synopsys, Inc., Austin, TX, USA

fYear

2014

Firstpage

1

Lastpage

3

Abstract

Challenges of a complex chip verification come from every aspect, such as network file system (NFS) access, coding style etc. This paper presents some best practices from several sytem-on-chip (SoC) and processor projects we completed recently. It includes: improve NFS access during regression, save and restore technologies for simulation and interactive debug, compilation technologies based on design partitioning and pre-compiled design units, a mixed-signal co-simulation environment involving both UPF based low power RTL simulation and transistor level simulation, etc. These best practices improved the verification productivity and helped us to complete the projects successfully on schedule.

Keywords

electronic engineering computing; flip-flops; formal verification; logic design; microprocessor chips; system-on-chip; NFS access; SoC; UPF based low power RTL simulation; coding style; complex chip verification; mixed-signal cosimulation environment; network file system; processor project; sytem-on-chip; transistor level simulation; verification productivity; Analytical models; Best practices; Databases; Graphical user interfaces; Runtime; Servers; System-on-chip; Mixed-signal Low Power co-simulation; Partition Compilation; Pre-Compiled Design; Processor Verification; Simulation Program Relocation; SoC Verification;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification Workshop (MTV), 2014 15th International

ISSN

1550-4093

Type

conf

DOI

10.1109/MTV.2014.16

Filename

7087224