An FPGA Based Ecosystem for USBPHY Validation

SOCs are getting complex day by day which makes IP design reuse a key approach. To prove functional performance of the IP in SOC, stimulus is required which activates the particular feature of the logic and output is matched with the golden values. Real time experience shows that it is not feasible to test all the features of the IP in SOC, specially negative scenarios such as timeout while enumerating the device. In this paper we propose a novel Validation Framework which validates USBPHY-IP as slave controlled by prototype model implemented in FPGA. Modifications are made in IP as soon as bugs are found and after successful validation (zero bugs), IP finally occupies space into SOC. This approach is capable of checking all the features of USB 2.0 which are currently posing major challenges in SOC validation. This could be a systematic approach to root cause many issues because of the easiness to play with logic sitting inside FPGA. This paper discusses the challenges for USBPHY IP validation and addresses the issues using this innovative framework. Some of the results are presented in the form of case studies for 45nm silicon.