System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation

System-on-chip designs became complex. As such, tracing complex sequential circuits over many clock cycles is not a simple process any more. Due to that, many mistakes can be made while writing assertions. In this paper, a new effective methodology is proposed to debug errors in an assertion assuming that there is no error in the design or the test bench. The proposed methodology is based on an innovated propagate-and-repeat algorithm, an enhanced mutation model, and a new three-state visual representation. A multi-core processing utilizing an efficient event scheduling engine is used to speed up the methodology analysis time. Experimental results show the efficiency of the proposed methodology in determining the errors in the assertion and on providing more information on design behavior.