JTAG-AXI Debug IP with Performance Meter Mode

The typical multi core SOC of today faces several development constraints. While the process and methodology plans for a first pass silicon, it is not always guaranteed. A true SOC design team always plans for debug capability when the SOC samples arrive. A debug/Test solution should also not increase the complexity and schedule of design, verification and physical design process. The debug/Test solution discussed provides a method to debug/Test the SOC and at the same time cater towards measuring performance in debug mode. This paper is targeted for the IP and SOC design teams developing the debug architecture in a SOC. It focuses on simplifying the debug process. It focusses on SOC interconnect performance measurement in debug mode. This paper describes a debug/Test solution which can be used to debug a SOC. It provides for inbuilt interconnect path performance measurement in absence of processor based control. It also provides for the ability to provide sequencing in the interconnect transactions to simulate real time interconnect activity.