Title :
An open-loop differential time amplifier
Author :
Hye-Jung Kwon ; Ji-Hoon Lim ; Byungsub Kim ; Jae-Yoon Sim ; Hong-June Park
Author_Institution :
Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea
Abstract :
An open-loop differential time amplifier is proposed to achieve a large time gain up to 114 and a wide range of input time difference up to 3.6ns. The time gain is determined by the ratio of two bias current values with the slew-rate control method. The differential architecture reduces the rms noise of the output time difference by 45% and the mismatch calibration reduces the time offset by 85%. The time amplifier consumes 1.5mW at 100MS/s and 1.2V supply in a 0.13μm CMOS process.
Keywords :
CMOS analogue integrated circuits; differential amplifiers; CMOS process; bias current value; differential architecture; input time difference; mismatch calibration; open-loop differential time amplifier; output time difference; power 1.5 mW; rms noise; size 0.13 mum; slew-rate control method; time gain; voltage 1.2 V; Noise; Process control; Voltage control; open-loop; slew-rate control; time amplifier; time gain;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087553
