A 10-bit 20-MS/s dual-channel algorithmic ADC with improved clocking scheme

Author

Joo-Won Oh ; Yong-Sik Kwak ; Gil-Cho Ahn

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

2014

Firstpage

56

Lastpage

57

Abstract

A 10-bit 20-MS/s dual-channel algorithmic analog-to-digital converter (ADC) using an improved clocking scheme is presented. The proposed ADC employs amplifier sharing technique with a conversion time scaling to reduce area and power. To achieve further improvement of conversion time scaling, dedicated MDAC sampling capacitors scaled with the accuracy requirement of each cycle are used. The ADC implemented in a 0.18μm CMOS process achieves 59.6dB SFDR and 54.3dB SNDR while consuming 8.96 mW per channel from a 1.8-V supply voltage.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; clocks; digital-analogue conversion; operational amplifiers; CMOS process; MDAC sampling capacitors; amplifier sharing technique; analog-to-digital converter; conversion time scaling; dual channel algorithmic ADC; improved clocking scheme; power 8.96 mW; size 0.18 mum; voltage 1.8 V; word length 10 bit; Accuracy; Clocks; Size measurement; Analog-to-digital converter (ADC); algorithmic ADC; capacitor scaling; conversion time scaling; op-amp sharing;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087555

Filename

7087555