Title :
Asynchronous circuit design using new high speed NCL gates
Author :
Minsu Choi ; Byung-Ho Kang ; Yong-Bin Kim ; Kyung Ki Kim
Author_Institution :
Dept. Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO, USA
Abstract :
The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4×4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.
Keywords :
CMOS logic circuits; asynchronous circuits; integrated circuit design; logic design; asynchronous circuit design; delay insensitive null convention logic; energy consumption; high speed NCL gates; high speed asynchronous circuit; low area overhead asynchronous circuit; transistor level design; wire complexity; CMOS integrated circuits; Delays; Inverters; Logic gates; Topology; Transistors; Wires; NCL; asynchronous circuit; delay insensitive model; multiplier; null convention logic;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087561
