An 10-Gb/s pulse-mode I/O for on-chip 5-mm interconnect

This paper proposes a low-power pulse-mode I/O for an on-chip data link. To use low-area MOS-type AC-coupling capacitors and the high-bandwidth source-follower-type receiver front-end, the common-mode levels of the channels are set higher than the supply voltages of I/Os. The signal amplification and high-pass filtering function at the receiver were designed using standard logic gates and MOS-type resistors only. The proposed I/Os were realized in a 90-nm CMOS process at 10Gbps and with 5-mm of on-chip microstrip channels. A test chip revealed that the I/O occupies a total area of 0.0025 mm², consumes 3.4 mW at 1.2 V of supply voltage, equal to a power efficiency of 0.068 pJ/bit/mm.