25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS

A 25-Gb/s inductorless output buffer circuit with a pre-emphasis is proposed. We designed the circuit parameters according to the frequency characteristics of the emphasized signal. To confirm the advantages of the emphasis circuit, we fabricated an output buffer IC in a 65-nm CMOS process. The proposed circuit has a control voltage to adjust the emphasis amplitude according to the load outside the chip. Measurement results showed that the jitters were 40% lower with the emphasis circuit than without, indicating that our proposed configuration can be applied to the design of output buffer circuits for higher operation speed.