Title :
Analysis of dynamic voltage drop with PVT variation in FinFET designs
Author :
Yongchan Ban ; Changseok Choi ; Hosoon Shin ; Jaewook Lee ; Yongseok Kang ; Woohyun Paik
Author_Institution :
Syst. IC R&D Lab., LG Electron., Seoul, South Korea
Abstract :
In this paper we have analyzed vectorless dynamic voltage (IR) drops and characterized the impact of transistor-level PVT (process-voltage-temperature) variation and metal-level RC (resistance-capacitance) corner variation in FinFET SoC (system-on-a-chip) designs. The impact of systematic process variations on signal interconnects is also considered for analyzing the worst case voltage drop in our design. Then, we discuss factors that can affect the design closure metrics for power and voltage integrity.
Keywords :
MOSFET; electric potential; integrated circuit design; system-on-chip; FinFET designs; PVT variation; metal-level RC corner variation; power integrity; process-voltage-temperature variation; signal interconnects; system-on-a-chip designs; transistor-level PVT; vectorless dynamic voltage drops; voltage integrity; Asia; DVD; FinFETs; Libraries; Switches; System-on-chip; Wires; Dynamic voltage drop; FinFET; IR drop; PVT variation; SoC; power; systematic variation; vectorless;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087608
