A digital lock detector for a dual loop PLL

A digital lock detector capable of detecting frequency variations occurred during the operation of a digital filter of the detector is proposed. In this paper, the digital lock detector is applied to a dual loop PLL to give the frequency lock information to another PLL loop. The proposed lock detector with the PLL fabricated in a 0.13-μm CMOS process occupies 0.17-mm² and consumes 35-mW from a 1.2-V power supply. The measured frequency offset between two VCOs is 0.16-%.