Efficient hardware architecture for real-time Semi-Global Matching

In this paper we propose an efficient hardware architecture for real-time SGM (Semi-Global Matching). SGM has a robust characteristic than previous local stereo matching algorithms. But SGM requires high computational loads and extremely high memory bandwidth to store intermediate results. To overcome these problems, we have maximized data parallelism by adopting systolic array and pipelining. Also we have maximized internal memory recycling efficiency to minimize memory bandwidth. With this method, our architecture not only processes 32 frame of VGA disparity images per second at 100MHz operating frequency but also do not requires external memory to store intermediate data. Our architecture was implemented using Verilog HDL. Our circuit is composed of 529,200 logic gates and 2,030,784 bits internal memory. Disparity map of SGM circuit has been verified using the Middlebury test images and the average error rate is 6.22%.