DocumentCode
3586359
Title
A 6bit 550Ms/s small area low power successive approximation ADC
Author
Zhou Peng ; Chenxi Han ; Dongmei Li ; Zhihua Wang
Author_Institution
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2014
Firstpage
200
Lastpage
201
Abstract
This paper presents a new capacitor array architecture to achieve a 6 bit 550Ms/s energy-efficient SAR with 65nm CMOS, which also takes up smaller area than traditional SAR. The bypass logic is a key feature to speed up the SA algorithm. Dynamic logic is used in the critical path to accelerate the speed. The whole circuit is supplied with 1.2V voltage. Simulation results show that the SAR achieves ENOB of 5.72, power consumption of 3.12mW with sampling rate at 550Ms/s, input frequency at Nyquist frequency.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; capacitors; energy conservation; flip-flops; logic design; low-power electronics; power consumption; CMOS; ENOB; Nyquist frequency; SA algorithm; analog-to-digital converters; bypass logic; capacitor array architecture; dynamic logic; energy-efficient SAR; low power successive approximation ADC; power 3.12 mW; power consumption; size 65 nm; voltage 1.2 V; CMOS integrated circuits; CMOS technology; SAR ADC; bypass logic; capacitor array;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2014 International
Type
conf
DOI
10.1109/ISOCC.2014.7087643
Filename
7087643
Link To Document