Ultra-low power 12T dual port SRAM for hardware accelerators

Author

Bo Wang ; Jun Zhou ; Kim, Tony T.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2014

Firstpage

274

Lastpage

275

Abstract

Dual-port SRAMs improve the performance of various hardware accelerators. This paper presents a low voltage 12T dual-port SRAM for biomedical hardware accelerators. The proposed dual-port SRAM cell -decreases the disturbance of the common-row-access mode for improving the worst case stability issue and realizing ultra-low voltage operation. In addition, hierarchical bitlines and a virtual ground technique are employed to further lower the power and minimum operating voltage and power consumption. A 16 Kb 12T dual-port SRAM was fabricated in a 65nm CMOS process technology and showed successful dual-port SRAM operation down to 0.4 V in the common-row-access mode.

Keywords

CMOS memory circuits; SRAM chips; biomedical electronics; low-power electronics; CMOS process technology; biomedical hardware accelerators; common-row-access mode; dual-port SRAM cell; hierarchical bitlines; low-voltage 12T dual-port SRAM; size 65 nm; ultralow-power 12T dual-port SRAM; virtual ground technique; voltage 0.4 V; CMOS integrated circuits; Hardware; Performance evaluation; Ports (Computers); SRAM cells; System-on-chip; dual-port SRAM; ultra-low power;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087645

Filename

7087645