Re-visit blocking texture cache design for modern GPU

Texture cache plays a significant position in GPU design especially in a limited memory bandwidth environment such as mobile SoC system. In this paper, we evaluate the 6D blocking texture cache design through a sophisticated GPU simulator using DRAM memory model. Our experiment reveals that using a larger block can take advantage of the spatial locality of texel accesses, however, fetching a larger block which requires several burst runs in DRAM access, results in poor memory access efficiency. As a result, the block size used has to match with the DRAM burst length for the best memory access efficiency.