Analysis of on chip decoupling capacitor in the double-gate FinFETs with PEEC-based power delivery network

As the technology node has scaled down below 32 nm, the supply voltage has decreased to 1V and the current demands for active devices have increased. Therefore, the supply noise due to the IR drop in the power delivery network (PDN) has become a critical problem for robust circuit operation. Huge decoupling capacitors are introduced to overcome the supply voltage fluctuations. In this study, we investigate a 32-nm double-gate FinFET device for a decoupling capacitor in the PDN. The circuit designers can independently control both the gates in the double-gate FinFET. We compare the supply and ground noise reduction in the conventional planar CMOS and in various FinFET structures in a PEEC-based practical PDN and propose the best decoupling capacitor design strategy for double-gate FinFETs. The simulation results show that we can achieve an increased reduction in the supply voltage noise up to 50% by shorting the front gate and back gate together.