Memory efficient data structure for graph representation of DSPF netlist

This paper presents a memory efficient data structure for graph representation of a circuit described in detailed standard parasitic format (DSPF) netlist. The proposed data structure is designed for full-chip DSPF netlists of recent VLSI designs, which contain several hundred millions of elements. Experimental results using an industrial full-chip DSPF netlist of 25Gbytes, the implemented DSPF parser for the proposed data structure showed its ability to handle a full-chip DSPF netlist of a recent VLSI design.