An optimal power methodology through constrained register sharing

In this paper, we present a new optimal power methodology through constrained register sharing that can be used to optimize the power consumption in the synthesized data path. This paper is the first attempt to the high-level synthesis of constrained scheduling which computes for given number of clock domains. First, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, we show that the algorithm through constrained register sharing which lead to an increase in the number of register. As a results, the proposed algorithm can reduce power in order to share registers and interconnections connected to functional units, as much as possible. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.