A high performance low power implementation scheme for FSM

Finite state machine (FSM) takes an important part in digital logic system. FSMs partition is one of the effective methods in regards to low power technique. Most of time only one of sub-FSMs need to be clocked, consequently power is saved. In this paper, we propose a high performance algorithm based on state transitions probability and low complexity control logic to implement the partitioned FSMs. The cost from one sub-FSM to other sub-FSMs could be minimum, and the transitions probability in one sub-FSM should be maximum. Based on the low complexity of control logic, we further give an optimized hardware architecture for the partitioned FSM model. Our proposed scheme has been implemented by using tsmc 45 nm technology library. Experimental results show that an average power reduction of 59% has been obtained for a set of standard FSM benchmark circuits.