Title :
Toward a Self-Aware Codelet Execution Model
Author :
Zuckerman, Stephane ; Landwehr, Aaron ; Livingston, Kelly ; Guang Gao
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Delaware, Newark, DE, USA
Abstract :
Future extreme-scale supercomputers will feature arrays of general-purpose and specialized many-core processors, totaling thousands of cores on a single chip. In general, many-core chips will most likely resemble a "hierarchical and distributed system on chip." It is expected that such systems will be hard to exploit not only for performance, but will also need to deal with reliability issues, as well as power and energy issues. The Codelet Model is a fine-grain dataflow-inspired and event-driven program execution model which was designed to run parallel programs on a combination of such many-core chips into a supercomputer. Meanwhile, some on-going work is attempting to take into account user goals as well as resource usage and make the system "self-aware:" By using introspective means, this kind of research tries to have the system software modify the state of the overall system at run-time to satisfy the user goals. It is very likely that future extreme-scale systems will be in constant demand of different kinds of resources, may they be processing elements (general purpose or otherwise), bandwidth, power budget, etc. This paper takes the position that a potential solution to solve the resource management issue at this scale is a hierarchical and distributed self-aware system leveraging the fine-grain event-driven codelet threading model.
Keywords :
multi-threading; power aware computing; resource allocation; software reliability; system-on-chip; distributed self-aware system; distributed system on chip; energy issue; event-driven codelet threading model; event-driven program execution model; extreme-scale supercomputers; extreme-scale systems; fine-grain dataflow-inspired program execution model; general-purpose many-core processor; hierarchical self-aware system; hierarchical system on chip; many-core chips; parallel programs; power issue; reliability issues; resource management; resource usage; self-aware codelet execution model; specialized many-core processor; Computational modeling; Computer architecture; Conferences; Hardware; Parallel processing; Supercomputers; System software; Dataflow; Codelets; Self-Awareness; Resource Management;
Conference_Titel :
Data-Flow Execution Models for Extreme Scale Computing (DFM), 2014 Fourth Workshop on
DOI :
10.1109/DFM.2014.12