Low power LVDS transmitter design and analysis

This paper presents the design and analysis of high speed low-voltage differential signaling (LVDS) transmitter compliant with TIA-644-A standard, which can operate up to 1 Gb/s. The advantage of LVDS is that it supports high speed signaling as well as low power. Also, it doesn´t suffer from severe overshoots and under-shoots that are inherent to high speed rail-to-rail signaling standards. The transmitter presented here is designed to support dual supply integrated circuits where external (IO) supply voltage is 1.8V and internal (core) supply voltage is 1.0V. The circuit is implemented in 40nm CMOS process that offers one thick gate oxide device option and one thin gate oxide device option. In nominal operating conditions, this circuit consumes only 7mW static power. This design is easily portable to function for higher IO supply voltage (2.5V, 3.3V) as well with minimal changes in the circuit design. This circuit can achieve speeds up to 1.5 Gbps for higher supply voltages.