A review paper on 3-T Xor cells and 8-T adder design in Cadence 180nm

The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further improvement. Using the best improved version of 3-T XOR cell a Full Adder Circuits is designed. All the basic circuits and their improved versions have been implemented in Cadence Virtuoso for 180nm technology and 1.8v sources.