Title :
A review paper on 3-T Xor cells and 8-T adder design in Cadence 180nm
Author :
Khan, Afshan Amin ; Pandey, Shivendra ; Pathak, Jyotirmoy
Abstract :
The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further improvement. Using the best improved version of 3-T XOR cell a Full Adder Circuits is designed. All the basic circuits and their improved versions have been implemented in Cadence Virtuoso for 180nm technology and 1.8v sources.
Keywords :
adders; integrated circuit design; 3-T XOR cells; 8-T adder design; Cadence Virtuoso; basic circuits; driving capability; full adder circuits; multipliers; size 180 nm; threshold loss problems; voltage 1.8 V; Adders; Convergence; Logic gates; MOS devices; Power demand; Simulation; Threshold voltage; 3T-XOR; 8-T Adder; Threshold loss problem;
Conference_Titel :
Convergence of Technology (I2CT), 2014 International Conference for
Print_ISBN :
978-1-4799-3758-5
DOI :
10.1109/I2CT.2014.7092068
