Analysis of SRAM cell designs for low power applications

SRAM is a main part of cache, therefore its power consumption reduction has always been researched. The present work aims to reduce leakage power without affecting the logic state of SRAM cell. For achieving this subthreshold operation is carried out. Furthermore two different techniques are analyzed for the same namely forced stack transistor technique and sleep transistor technique. It is seen from the analysis that sleep transistor technique shows less average power dissipation compared to others whereas forced stack transistor technique gives minimum average delay compared to others. A convincing power reduction is achieved in a SRAM cell with minimum critical path delay using sleep transistor technique. Simulations are carried out using TSPICE for 90nm, 45nm and 32nm CMOS technology nodes. For subthreshold operation the supply voltage 0.35V is used.