High-throughput DOCSIS upstream QC-LDPC decoder

The newly released Data Over Cable Service Interface Specification (DOCSIS) 3.1 standard enables gigabit-speed broadband connection over cable television network. The main challenge at the upstream receiver is a computationally intensive LDPC decoder which need to achieve the 1Gbps throughput with low block error rates. In this paper, we present an implementation of the upstream LDPC decoder on Xilinx FPGA using the VIVADO high level synthesis tool. We show that the resulting design can achieve 1.43 Gbps throughput on a Xilinx Kintex7 XC7K480T FPGA at 204.8 MHz clock frequency with 24% device usage. To our knowledge, this paper presents the first hardware implementation of DOCSIS 3.1 upstream LDPC decoder on FPGA.