A high throughput and low power radix-4 FFT architecture

In this paper, a high throughput and low power architecture for 256-point FFT processor is proposed which is suitable for both high performance and low power applications. The proposed architecture is based on Radix-4 algorithm. We choose pipelined Multi-path Delay Commutators (MDC) for our design. Two separate datapaths are used in this architecture so that it can process eight inputs in parallel. Thus, the throughput is increased by eight times while achieving 100% hardware utilization. Power consumption of this architecture is shown to be about 50% less than a regular Radix-4 MDC structure for a same throughput. We implement our design in Xilinx FPGA Virtex 5 and compare with regular R4MDC for area, throughput, and power.