Title :
A high throughput and low power radix-4 FFT architecture
Author :
Mookherjee, Soumak ; DeBrunner, Linda ; DeBrunner, Victor
Author_Institution :
Electr. & Comput. Eng., Florida State Univ., Tallahassee, FL, USA
Abstract :
In this paper, a high throughput and low power architecture for 256-point FFT processor is proposed which is suitable for both high performance and low power applications. The proposed architecture is based on Radix-4 algorithm. We choose pipelined Multi-path Delay Commutators (MDC) for our design. Two separate datapaths are used in this architecture so that it can process eight inputs in parallel. Thus, the throughput is increased by eight times while achieving 100% hardware utilization. Power consumption of this architecture is shown to be about 50% less than a regular Radix-4 MDC structure for a same throughput. We implement our design in Xilinx FPGA Virtex 5 and compare with regular R4MDC for area, throughput, and power.
Keywords :
fast Fourier transforms; field programmable gate arrays; low-power electronics; pipeline arithmetic; FFT processor; MDC; Xilinx FPGA Virtex 5; area factor; datapaths; hardware utilization; high-performance application; high-throughput low-power radix-4 FFT architecture; low-power application; pipelined multipath delay commutators; power consumption; throughput factor; Complexity theory; Computer architecture; Delays; Field programmable gate arrays; Hardware; Power demand; Throughput; 2-parallel; DIF; DSP; FFT; R4MDC;
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
DOI :
10.1109/ACSSC.2014.7094663
