Dynamically reconfigurable multi-processor arrays

In this paper, the FPGA-based Multi-Processor Array architectural form is augmented with capability for hardware partial reconfiguration on processor element I/D-space memory components. Reconfiguration overhead is effectively masked on the process schedule timeline with use of an associated pipelining mechanism. In this manner, a maximally-parallel processing gain may be achieved. The resulting structure is then leveraged in support of a spatiotemporal processing model applicable to arbitrarily large dataflow graphs.