Field-order based hardware cost analysis of non-binary LDPC decoders

Non-binary low-density parity-check codes exhibit excellent coding gain at the cost of decoding complexity. Furthermore, the effects of the Galois field order on the hardware cost have not been well established. We propose a modification to the Min-Max algorithm to simplify calculations while maintaining decoding performance. In addition, a hardware area efficiency analysis is proposed, allowing a quantified exploration of the decoder design space. This analysis reveals that the proposed algorithm yields multiple choices: a GF(4) decoder with 2x hardware efficiency or a GF(8) decoder with 1dB coding gain, relative to the original algorithm in GF(4).