Dynamically Adaptive Header Generator and front-end source emulator for a 100 Gbps FPGA based DAQ

To handle the expected increase in data rate of the LHCb experiment after the upgrade, a new FPGA based DAQ system has been proposed. As a part of this new DAQ system a Dynamically Adaptive Header Generator has been designed and implemented to packetize the streaming data coming, from the Front-end electronics of the detectors, for easy access and processing by the Servers. This module also dynamically generates a new data stream by dropping datasets in a controlled fashion in the event of receiving a back pressure signal from the downstream modules. This paper details an architecture that address the need for a DAQ system that effectively balances the 3 conflicting requirements of Real-time operation, Data Integrity and System stability. A synthesizable Front-End Source Emulator has also been implemented to generate data patterns required to test the Header Generator module. This can be used as a test bench for the Header Generator module or a as a standalone module that can be integrated with other systems as required. A system comprising of both the Source Emulator and the header Generator have been implemented on an Altera Stratix IV device and the results discussed.