Reliable and redundant FPGA based read-out design in the ATLAS TileCal demonstrator

The Tile calorimeter at ATLAS [1] is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector, before transfer to the counting room. The on-detector electronics will be replaced around 2023. The higher radiation levels expected when the beam luminosity is increased require radiation tolerant components. To achieve the required reliability the upgraded system must be highly redundant. To provide flexibility the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Within a year, a “demonstrator" with the new read-out system will be installed in ATLAS, replacing one slice of the Tile calorimeter. This will allow the upgrade proposed for 2023 to be thoroughly evaluated well before deployment in all TileCal slices. Different firmware strategies alongside with their integration in the demonstrator will be presented in the context of high reliability protection against hardware malfunction and radiation induced errors.