A frequency agile, self-adaptive serial link on Xilinx FPGAs

Modern FPGA devices, with high-speed multi-gigabit transceiver resources, together with great amount of logic gates, clock conditioning modules, availability of RAM memory blocks and re-programmability on the field, are among the most widely used electronics components in the Trigger and Data Acquisition systems in High Energy Physics (HEP) experiments.We focused on the Xilinx Kintex 7 FPGAs and, specifically, on the GTX transceiver modules, which provide high bandwidth, low transmit jitter and efficient auto-adaptive equalization system both on the transmitter and the receiver. A remarkable characteristic of the Xilinx GTX is the presence of reconfigurable ports, which allow to modify some parameters on-the-fly, such as the line rate, and the horizontal and vertical offset from the data sample point in the GTX receiver. This functionality represents the base mechanism to perform a 2-D eye-scan, thus allowing to control the quality of the received data and to easily calculate the Bit Error Rate (BER) from the eye diagram. In this paper, we present a frequency agile, auto-adaptive serial link. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to perform a 2-D eye-scan and takes care of the reconfiguration of the GTX parameters, in order to fully benefit from the available link bandwidth.