Title :
System-level chip/package co-design for multi-core processors implemented with power-gating technique
Author :
Chenyun Pan ; Mukhopadhyay, Saibal ; Naeemi, Azad
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Based on a system-level design methodology and a modified power delivery network model, optimization and benchmarking are performed for a processor implemented with the power-gating technique under various package configurations. Optimal widths of the sleep transistors are obtained based on how frequently the processors need to switch between active and idle state. Up to 75% of the energy-delay product saving is observed for the processors using power-gating technique with a low switching frequency. Additionally, the optimal position of the decap insertion is demonstrated to be application dependent.
Keywords :
integrated circuit design; microprocessor chips; multiprocessing systems; power aware computing; transistors; decap insertion position; energy-delay product saving; modified power delivery network model; multicore processors; power-gating technique; sleep transistors; switching frequency; system-level chip-package co-design; Decision support systems; Design methodology; Noise; Optimization; Switching circuits; Throughput; Transistors; decap; noise; package; power delivery network; power-gating; system-level co-design; throughput;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN :
978-1-4799-3641-0
DOI :
10.1109/EPEPS.2014.7103580
