DocumentCode
3588969
Title
A study of split and common ground referencing schemes for a high speed bus
Author
Tingdong Zhou ; Wenzel, Robert
Author_Institution
Digital Networking Group, Freescale Semicond., Austin, TX, USA
fYear
2014
Firstpage
15
Lastpage
18
Abstract
Two different module referencing schemes, one with split ground planes between transmit/receive (TX/RX), and the other with a common ground plane, are first compared using models generated from 3D full-wave solver, and then the two different module designs are built and tested. The measurements performed and test data on the manufactured modules includes TX output high-low amplitude, eye height, RX jitter tolerance, Phase-Lock-Loop (PLL) interference, and jitter transfer function testing for the transmitter. The data indicates that the common ground referencing scheme results in superior performance for the high speed interface.
Keywords
integrated circuit design; integrated circuit testing; system-on-chip; 3D full-wave solver; PLL; RX jitter tolerance; TX output high-low amplitude; common ground plane; common ground referencing schemes; eye height; high speed bus; high speed interface; jitter transfer function testing; module designs; module referencing schemes; phase-lock-loop interference; split ground planes; split ground referencing schemes; system-on-chip; transmitter; Clocks; Crosstalk; Frequency measurement; Jitter; Phase locked loops; Receivers; Transmitters; Crosstalk; Jitter; Phase-lock-loop (PLL); Serializer/Deserializer (SerDes); Signal integrity;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN
978-1-4799-3641-0
Type
conf
DOI
10.1109/EPEPS.2014.7103581
Filename
7103581
Link To Document